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| HV9605 HV9605 Preliminary High Voltage Current Mode PWM Controller for ISDN Equipment Ordering Information +VIN Min 15V Max 250V Feedback Accuracy < 1% Max Duty Cycle 49% 14 Pin Plastic DIP HV9605P Package Options 14 Pin Narrow Body SOIC HV9605NG Die HV9605X Features BiCMOS/DMOS technology Current mode control 49% duty cycle operation Programmable START/STOP capability 15V to 250V input range internal start-up regulator 6.0A standby supply current for +VIN <20V 0.9mA operating supply current 5.0V V DD supply operation 30KHz to 300KHz internal oscillator 15KHz to 150KHz converter output frequency 1.0MHz low offset error amplifier 1.20V 2% band gap reference Output driver optimized for under 10W applications Low driver output impedance with VDD = 0V Fast (90nsec) over current shutdown All pins are ESD protected General Description The Supertex HV9605 is a BiCMOS/DMOS single-output, current mode, pulse width modulator IC designed to meet the requirements of ETR-060 for ISDN applications. In a 14 pin package, it provides all the necessary functions to implement a single-switch PWM with a minimum of external parts. Utilizing Supertex's proprietary BiCMOS/DMOS technology, it requires less than one tenth of the operating power of conventional bipolar PWM ICs. Dynamic range for regulation is also increased to approximately 8 times that of similar bipolar parts. It operates directly from any DC input voltage between 15 and 250 VDC. The START and STOP input voltage thresholds can be programmed within the operating input voltage range by means of a resistor divider, provided +VIN(START) > +V IN(STOP). The output stage is push-pull CMOS, eliminating the need for external clamping diodes. The clock frequency is set with a single external resistor. Applications ISDN network terminations ISDN terminals ISDN terminal adapters Feature phones SLIC circuits PBX systems Modems Distributed power systems DC/DC converters 11/30/98 Absolute Maximum Ratings* +VIN, Input Voltage Supply Voltage, V DD Operating Temperature Range Storage Temperature Range Power Dissipation @ 25C, SOIC Power Dissipation @ 25C, Plastic DIP *All voltages referenced to GND -0.5V to +250V -0.5V to +10V -40C to +85C -65C to +150C 750mW 1000mW Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 11/30/98 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For complete liability information covering this and other Supertex products, refer to the Supertex 1998 Databook. 1 HV9605 Electrical Characteristics Symbol Parameters Min Typ Max Unit Conditions Pre-Regulator/Start-Up +VIN +IIN +IIN +ISTART VDD UVLO HYST Regulator input voltage Input leakage current Input leakage current Pre-regulator start-up current Regulator output voltage Under voltage lockout threshold Under voltage hysteresis 5.0 4.4 4.1 0.1 4.5 4.2 0.3 4.6 4.4 0.4 15 250 6.0 50 V A A mA V V V VDD rising +VIN=20V, Start=0V, Stop=0V +VIN = 250V, VDD = 4.7V +VIN = 15V, Start & Stop 10M to + VIN Supply VDD IDD Operating range Supply current 4.7 0.9 8.0 1.3 V mA OUT open, fOUT = 20KHz to 150KHz, VDD = 5V Start/Stop Control VSTART ISTART ISTOP VCLAMP Start threshold Start input current Stop input current Zener clamp voltage on STOP Pin 20 6.72 7.30 7.88 0.05 0.05 V A A V +VIN = 18V +VIN = 18V MOSFET Driver Output VOUT(HIGH) VOUT(LOW) tR tF Output high voltage Output low voltage Rise time Fall time 4.85 4.90 0.05 30 20 0.15 50 50 V V nsec nsec IOUT = 10mA, VDD = 5.00V IOUT = -10mA CL = 250pf CL = 250pf Oscillator 150 fOUT Output converter frequency 45 31.5 18 TC f/f Temperature coefficient Voltage stability 50 35 20 100 1 55 38.5 22 300 3 KHz KHz KHz KHz PPM/C % RT = 91K RT = 390K RT = 560K RT = 1.0M fOUT = 50KHz fOUT = 50KHz, 4.5V< VDD<5.5V 11/30/98 2 HV9605 Electrical Characteristics Symbol Parameters (continued) Min Typ Max Unit Conditions PWM DMAX DMIN Maximum duty cycle Minimum duty cycle Minimum pulse width before pulse drop out 80 49.0 49.9 0 125 % % nsec fOUT = 20KHz Reference VREF VREF VREF VREF IREF(SHORT) Reference output voltage Load regulation Line regulation Reference output voltage Long term stability Short circuit current 1.159 1.176 1.200 1.0 2.0 1.200 3.0 0.5 1.0 1.224 5.0 5.0 1.241 V mV mV V mV mA TA = 25C 0 < IREF < 0.3mA 3.0V < VDD < 5.5V -40C < TA < 85C TA = 125C, 1000hrs VREF = SGND Current Sensing VCS VCS (LIMIT) tDELAY Usable control current sense range Current limit threshold Current limit delay to output 0.6 0.7 90 VCS (limit) 0.8 120 V V nsec VCS = 1.5V Error Amplifier VFB IFB or INI VOS VCM AVOL BW ISOURCE ISINK PSRR Feedback voltage Input bias current Input offset voltage Common mode input range Open loop voltage gain Unity gain bandwidth Output current sourcing Output current sinking Power supply rejection 2 50 0 65 1.0 90 1.5 -2 4 72 -1 1.188 1.200 25 5.0 1.212 200 25 VDD-1 V nA mV V dB MHz mA mA dB VFB < VNI VFB > VNI 4.5V < VDD < 5.5V, f=1KHz REF shorted to NI, FB shorted to Comp, TA = 25C VFB = 3.0V, VNI = 2.5V Status Output ISINK ISOURCE VSTATUS(LOW) Output current sinking Output current sourcing 5.0 5.0 VDD-0.2 1.0 0.02 tR Rise time 1.0 5.0 10 10 15 VDD 2.0 0.04 mA A V V V msec No load Sinking 5mA Sinking 100A 4.7nF From Status to GND VSTATUS = 2.0V VSTATUS(HIGH) High output voltage Low output voltage 11/30/98 3 HV9605 Pin Description SGND - Common connection for all low level signal and digital circuits. While SGND and PGND must be electrically connected together, having separate common pins enhances the ability of the designer to prevent coupling of noise into critical circuits. PGND - This pin provides common return for the high transient current of the output driver circuits. While PGND and SGND must be electrically connected, having a separate connection prevents common noise created by the high transient currents of the output driver from being injected into critical circuits. +VIN - This is the start-up linear pre-regulator input which can accept DC input voltages in the range of 15V to 250V. With START and STOP set to more than 20V, the leakage current on this pin is less than 6.0A at +VIN = 20V. START - The resistive divider from +VIN sets the start voltage. STOP - The resistive divider from +VIN sets the stop voltage. - This is the supply pin for the PWM circuits. When the VDD input voltage to the +VIN pin exceeds the start voltage the input regulator seeks to regulate the voltage on the capacitor connected to this pin to a nominal 4.5V. OUT - This high current push-pull CMOS output is intended to drive the gate of a power MOSFET. In order to protect the power MOSFET in high electrical noise environment, this output appears as low impedance to PGND when VDD is at zero volts. CS - This is the current sense input to the PWM comparators. Under normal operation the over current limit is triggered when the voltage on this pin is at 0.70V and the loop control operating peak current may be set to any level below this, typically in the range of 0.2 to 0.5V. COMP - The low impedance output of the error amplifier. FB NI - The high impedance inverting input of the error amplifier. - The high impedance non-inverting input of the error amplifier. REF - This pin provides a 2% accuracy 1.20V low output impedance buffered reference which is current limited to 0.5mAmps and should be bypassed, REF to SGND, with a 0.1F ceramic capacitor. RT - The resistor connected from this pin to SGND sets the frequency of the internal oscillator by setting the charging current for the internal timing capacitor. The oscillator frequency is twice the PWM output frequency. STATUS - This output is held low until the +VIN voltage reaches the programmed START voltage. It remains low until the bootstrap supply to VDD forces the voltage above the internal regulator set point. It is further held low while the control amplifier output on the COMP pin is forced to its high limit by a low output from the converter. Once all these conditions are satisfied, this output will rise to VDD with a time constant set by the external capacitor indicating that normal operation has been reached. This output may be used to control the reset of a microprocessor. Pin Configuration +VIN STOP START REF VDD PGND CS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 COMP FB NI STATUS RT SGND OUT 14 Pin SOIC/DIP Package 11/30/98 4 HV9605 Functional Block Diagram +VIN STOP Start-Up Regulator + VDD H=SWITCH CLOSED L= SWITCH OPEN Enable UVLO C VREF START + - - C VSTART Bootstrap Good PWM Good STATUS MOSFET Driver VDD Clock Oscillator CLK Q D Q CLR SQ + OUT A - - C + R CS PGND SGND VDD Bandgap Reference Generator RT REF NI FB COMP Typical Application Circuit HV9605 + 48V INPUT VDD STATUS OUT CS PGND SGND COMP +5.0V REFERENCED TO INPUT (-) TERMINAL TN2124K1 or TN2524N8 + +VIN STOP START + + + 40V + ISOLATED OUTPUT RESET RT REF NI FB 11/30/98 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 745-4895 www.supertex.com 11/30/98 |
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